I think the key for you will be to determine the layout of your internal memory array. For reference I use an Intel i7 K 3. The following is the initial few lines from the MEM file I used: My recommendation at this time, is that if you can tolerate the performance degradation that occurs when LUT-based multiplexers are used to select the correct x 8 RAM, then use a x8 bit lane assignment. Approaching the Finish Line I am getting close to finishing my part of the project, and only have a week and a half left for this internship period. I have also used the SmartXplorer tool to find ways to keep project speeds maintained MHz in the past. In other words, the block RAMs in my current project can only be arranged in one form to provide the x 12 arrangement that I require, and I haven't determined if this arrangement is dictated by the synthesizer, or implemented by the placer. Uploader: Molkree Date Added: 24 March 2012 File Size: 3
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